A variety of techniques have been employed to achieve device isolation in integrated circuitry. These include junction isolation, formation of channel stops with dopant implants and the inclusion of dielectric material, e.g., by local oxidation of silicon. For the silicon planar process the class of dielectric isolation commonly referred to as silicon on insulator (SOI), is used to form individual devices on discrete islands or mesas. Advantages of SOI technology include improved power handling capability, avoidance of latch-up problems associated with junction isolation, and improvements in transistor operating frequency, the latter resulting from lower output capacitance attributable to the dielectric isolation. Generally SOI structures exhibit greater tolerance and immunity to the effects of ionizing radiation and, therefore, are the structure of choice for rad hard environments.
In the past, such dielectrically isolated islands have been formed by thermally growing an oxide layer on a silicon wafer surface and then depositing a relatively thick layer of polycrystalline silicon (polysilicon) over the oxide. The polysilicon layer, sometimes referred to as the handle, is relied upon to provide structural integrity to the overall wafer during subsequent processing. The silicon wafer material is frequently thinned to a thickness of less than 1 mil and polished to provide a starting material for epitaxial silicon growth. This technique is characterized by relatively high temperature processing, consequent high levels of mechanical stress, lattice damage and various nonuniformities across the wafer. See, however, U.S. Pat. No. 4,554,059, assigned to the assignee of the present invention, which teaches an electrochemical technique for improving the wafer yield of integrated circuits formed with dielectrically isolated islands.
Several other SOI techniques are of current interest. These include Separation by IMplantation of OXygen (SIMOX), Zone Melt Recrystallization (ZMR), Full Isolation by the Porous Oxidation of Silicon (FIPOS), Silicon on Sapphire (SOS) and bonded wafers. At this time, SOS and bonded wafer technology have advanced sufficiently to realize commercial feasibility.
A feature common to all of the aforementioned SOI technologies is the relatively low thermal conductivity characteristic of the insulator material. Thus, design considerations based on upper limits for steady state operating temperatures of active devices frequently require inclusion of a cooling zone, i.e., additional heat dissipation volume, within each device island. In addition to having a significant impact on the achievable level of device integration, the added volume of semiconductor material can increase parasitic capacitance thereby degrading overall circuit performance. By way of example, consider that the area size of a bipolar transistor island permits a predetermined level of power dissipation beyond which the operating temperature becomes undesirably high relative to ambient conditions. For one known geometry with island dimensions of 51 microns by 43 microns, a temperature rise on the order of 1.degree. C. will occur with 1.5 mW of steady state power dissipation. In order to increase the power dissipation to 3.75 mW, while still limiting the temperature to 1.degree. C. above ambient, it becomes necessary to increase the island dimensions to 81 microns by 73 microns. That is, approximately 2.5 times the surface area is required in order to dissipate the additional heat. In circuits employing high speed transistors, the required cooling zone can impart other undesirable effects such as parasitic collector-substrate capacitance. Such capacitance such can reduce the circuit frequency response by 20%.
From the above it is apparent that competing demands for increased power handling capability and higher levels of device integration require application specific tradeoffs. This is particularly problematic in view of the current trends to develop standard cell libraries and device arrays each suitable for a wide variety of applications.